Reed-Solomon encoding may be implemented in circuitry using matrix multiplication logic. An implementation based on matrix multiplication, whether in a Field Programmable Gate Array (FPGA), PLD, or other logic device, allows a Reed-Solomon encoder to run at a maximum device frequency. Further, a multiplication-based implementation reduces or eliminates feedback paths that are normally required in a division-based implementation so that data may be pipelined to increase an effective data throughput.
While multiplication-based Reed-Solomon encoding may be pipelined to match a desired data rate, multiplication-based implementations generally require a significant amount of logic, for example, a significant number of adaptive look up tables (ALUTs). For example, the IEEE 802.3 standard specifies hard and soft forward error correction at throughputs of four channels at 25 gigabits per second (Gb/s), four channels at 28 Gb/s, and one channel at 100 Gb/s. A conventional multiplication-based Reed-Solomon encoder pipelined to achieve these data throughputs may use on the order of 30,000 ALUTs, which entails significant cost, power, and device area requirements.